To reduce power during operation of circuits of a computer, semiconductor or the like, a method of controlling the clock to necessary and sufficient frequencies is known. The clock frequency is raised for processing that needs a fixed level of performance or more or high-load processing to avoid damaging a function. Conversely, the clock frequency is lowered to reduce power during operation for processing that does not need performance or low-load processing.
If any operating condition such as the temperature or the maximum current amount permitted by a circuit is set, the control to lower the clock frequency is exercised for operation within the range of the operating condition. In such a case, however, performance is sacrificed and it becomes difficult to satisfy the function that should originally be provided.
In general, to control the clock frequency, a method of generating a plurality of clocks in advance and switching the clock or a method of exercising setting change control of a clock generator such as a phase locked loop (PLL) or a frequency division circuit capable of taking a plurality of division ratios is adopted. In this case, problems such as the switching time of clock, area overheads of a circuit and the like arise.
If it takes time to switch the clock, an operation at an optimum clock frequency cannot be performed. For example, wasteful power is consumed by an operation on a high-frequency clock in a period in which a low-frequency operation is allowed. Conversely, a low-frequency clock is supplied in a period in which an operation at high frequencies is required, inviting lower performance.
Compared with other blocks, a clock generator is a block of high operation rate and when area overheads arise, the overheads could become a factor that prevents an originally intended reduction of power from being achieved.